Metric Description
Throughout the memory hierarchy, data moves at cache-line granularity (64 bytes per line). Although this is much larger than many common data types (such as integer, float, or double), unaligned values of these or other types may span two cache lines. Recent Intel® architectures have significantly improved the performance of such 'split loads' by introducing split registers to handle these cases. But split loads can still be problematic, especially if many split loads in a row consume all available split registers.
Parent topic: CPU Metrics
See Also
Supplemental documentation specific to a particular Intel Studio may be available at <install-dir>\<studio>\documentation\ .
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