Viewing the result of an Intel® Xeon™ Phi coprocessor analysis is similar to viewing results collected on the host system. These are some tips useful for viewing the data collected on the Intel Xeon Phi coprocessor.
Viewing Inline Functions
Intel® VTune™ Amplifier enables you to view performance data of inline functions for compiler-optimized applications with symbols. To enable this feature, use the Intel Compiler switch -debug intel-debug-info. By default, the VTune Amplifier displays inline functions (virtual frames) as regular functions. To view all instances of the inline function in one row, select the Source Function/Function/Call Stack level in the Grouping menu. Note that virtual frames may be structured as call stacks, but this is just a display of the inline functions nested within their calling functions. Call stack view is not supported for applications targeted for Intel Xeon Phi coprocessor.
To disable displaying inline functions, select off from the Inline Mode drop-down menu on the filter toolbar.
Viewing Threads on the Timeline
To view performance data provided in the Timeline pane, right-click, select the Change Band Height context menu option and select the Tiny display mode. It helps view large numbers of threads that are typical for high-end parallel applications targeted for Intel Xeon Phi coprocessors. This mode sets a minimal row height (about 6 pixels) and shows limited graphs of event data. If there are data, the active ranges are colored: the more data associated with a pixel, the more intense color is used for drawing. Otherwise, the band is shown in a regular background color.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |